São Paulo, 09 de Setembro de 2007
Vários são os modelos e formatos utilizados nas publicações de papers. Cada editor normalmente adota um formato próprio visando padronizar o texto produzidos pelos autores, conforme alguns padrões adotados em suas revistas.
De um modo geral todos os papers apresentam um esquema baseado em tópicos que deverão estar presentes no texto final (Full Papper). Segue abaixo o conjunto de tópicos presentes na maioria dos papers, e em especial, os publicados no IEEE.
- Título
- Autores
- Palavras chaves (keywords)
- Resumo
- Introdução
- Descrição
- Metodologia
- Análises e/ou Camparações
- Conclusão
- Agradecimentos
- Referências
Os tipos das fonte de caracteres, os alinhamentos das títulos e subtítulos, dos gráficos e figuras e da bibliografia, dependem muito particularmente dos editores. Normalmente, um template é fornecido pelo editor para facilitar a padronização estética da aprensetção final do paper. Esse template nada mais é do um arquivo em .pdf ou .doc que apresenta uma visão geral do modelo que será considerado pelo editor.
Para ilustrar com um paper deve ser formatado vejamos um exemplo prático de um artigo publicado nas Revistas do IEEE. O artigo A VLSI Architecture for Image Registration in Real Time, foi publicado no IEEE Transactions on Very Large Scale Integration Systems, Vol. 15 Nº 9 de Setembro de 2007 e apresenta a seguinte estrutura de texto.1. Título
A VLSI Architecture for Image Registration in Real Time
2. Autores
Nisheeth Gupta, Member, IEEE, and Nikhil Gupta, Member, IEEE
3. Resumo
"Abstract—Image registration is an ubiquitous task occurring in countless image analysis applications. A dedicated implementation of image registration algorithms is the best approach to meet the intensive computation requirements of implementing image registration schemes in real time. This paper presents an efficient VLSI architecture for real-time implementation of image registration algorithms using an exhaustive search method. Normalized cross correlation function, mean square error, and blue screen technique algorithms are implemented for image registration. The architecture is based on a data flow design that allows sequential inputs but performs parallel processing. Based on the architecture, a programmable chip can be designed for image registration. Chips can be cascaded to achieve better performance and sizes of both the search and the reference image which can vary with time from a small to a very large value."
4. Palavras chaves (keywords)
"Index Terms—Blue screen technique, image registration, mean square error (MSE), normalized cross-correlation function (NCCF), tracking, VLSI architecture. "
5. Introdução
"I. INTRODUCTION
APOWERFUL vision-based system for image registration is of growing interest in many digital image processing applications such as medical imaging, industrial imaging, robot vision, tracking an area of interest before detection, tracking point targets, and multitarget handling capability. Image registration requires precise location of the reference image within the search image. Until now, the usage of these algorithms has been strongly limited due to their very high computational requirements. In addition, real time and space constraints increase the performance requirements on the computing engine...."
6. Descrição
"II. IMAGE REGISTRATION ALGORITHMS IMPLEMENTED
The problem of locating a reference image within a larger image is called image registration. Image registration can be depicted as shown in Fig. 1. Let the search image and the reference image be of and pixels, respectively. Let be the subimage of starting at (i,j)...."
7. Metodologia
"III. ARCHITECTURE AND ITS DATA FLOW
In the proposed architecture, rc and rr loops (lines 3 and 4 in Fig. 2) are performed in parallel, and therefore, it is necessary to have M2 window processors (WP) for a reference block of M x M pixels. The data flow of the proposed architecture is based on [8], but with a higher number of WPs...."
8. Análises e/ou Comparações
"V. PERFORMANCE ANALYSIS AND COMPARISON
As different image registration schemes may use different image sizes and thus may require varying tracking ranges, the proposed architecture has been designed to offer flexibility in size of both the search and the reference image...."
9. Conclusão
"VI. CONCLUSION
A newclass of fully parameterizable architecture for real time image registration is proposed in this paper. By computing several coefficients in parallel, the proposed architecture is capable of speeding up NCCF, MSE, and even the extended version of widely used NCCF-BST. The proposed architecture allows serial input but performs parallel processing based on systolic
array design. The architecture supports both cascaded and noncascaded chip configuration...."
10. Agradecimentos
"ACKNOWLEDGMENT
N. Gupta would like to thank B. V. Rao and K. V. Sujatha from Imaging Infrared Division, RCI, Hyderabad, India, for their constant support, fruitful suggestions, and discussions...."
11. Referências
"REFERENCES
[1] P. F. Aschwanden, “Experimenteller Vergleich uon Korrelationskriterien. in der Bildanalyse,” Ph.D. dissertation, Promotion, Hartung-Gorre Verlag Konstanz, ETH Zurich, Zurich, Switzerland, 1993.
[2] SV. R. Kumar et al., “Architectures for real time image registration,” presented at the Int. Symp. Opto-Electron. Imaging, New Delhi, India, 1985...."
